Apparatus and method for transporting/receiving data in a CDMA mobile communication system

ABSTRACT

Disclosed is a data transportation/reception apparatus and method in a mobile communication system. The data transportation apparatus and method divides transport data bits into bits having higher priority and bits having lower priority, maps the bits having higher priority to bit positions having higher reliability, and maps the bits having lower priority to bit positions having lower reliability. The data reception apparatus and method demodulates received modulated symbols, divides the demodulated coded bits into two coded bit groups according to priority, deinterleaving the coded bit groups using different deinterleavers, and decodes the deinterleaved coded bits.

PRIORITY

[0001] This application claims priority to an application entitled“Apparatus and Method for Transporting/Receiving Data in a CDMA MobileCommunication System” filed in the Korean Industrial Property Office onApr. 4, 2001 and assigned Serial No. 2001-17925, the contents of whichare hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to an apparatus andmethod for transporting/receiving data in a CDMA (Code Division MultipleAccess) mobile communication system, and in particular, to a datatransportation/reception apparatus and method for improving reliabilityof transport data bits.

[0004] 2. Description of the Related Art

[0005] In a communication system, it is actually impossible to receive atransported signal without any distortions or noises. In particular,when the signal is transported/received over a wireless network, theeffects of the distortions or noises are more serious as compared withwhen the signal is transported/received over a wired network.

[0006] Therefore, many efforts have been made to minimize the effects ofthe distortions or noises. An error control coding technique has beenproposed as a typical method of minimizing the effects of thedistortions or noises. Codes used for the error control coding techniqueare classified into a memoryless code and a memory code. For example,the memoryless code includes a linear block code, while the memory codeincludes a convolutional code and a turbo code. A device for generatingsuch codes is called a “channel encoder”, and its outputs can be dividedinto systematic bits and parity bits based on the error control codingtechnique. The turbo code is a code typically used for the error controlcoding technique that separates its outputs into the systematic bits andthe parity bits. In addition to the turbo code, there exists asystematic convolutional code of the convolutional code, as a code usedfor the error control coding technique.

[0007] Herein, the “systematic bits” mean an actual transport signal,while the “parity bits” mean a supplemental signal added to correct apossible error which occurred during transportation in a decodingprocess. However, even though a signal is subjected to the error controlcoding, if a burst error occurs in the systematic bits or the paritybits, it is not easy to correct the burst error. Such a phenomenonfrequently occurs while the signal passes through a fading channel, andan “interleaving” technique is typically used to prevent thisphenomenon. The interleaving technique disperses a damaged part inseveral places rather than concentrating it on a single place, therebycomplementing the error control coding technique.

[0008] Such interleaved signal is subject to mapping in a symbol unit ina digital modulator. The number of bits included in one symbol increaseswith the order of the modulator. Particularly, in the case of high-ordermodulation of over 16QAM (16-ary Quadrature Amplitude Modulation), onesymbol includes information of over 4 bits, and the bits can beclassified according to reliability. Here, the “reliability” can berepresented by a probability that the bit values will be changed duringtransportation. For example, when one 16QAM-modualted symbol is subjectto mapping on coordinates, information of leading two bits in the symbolhas higher reliability since the leading two bits determine a quadrantof the coordinates, to which the symbol is to be mapped. This means thatthere is a lower probability that the information of the leading twobits will be changed during transportation. However, information of theremaining two bits in the symbol has lower reliability, since theremaining two bits determine one of the four regions obtained bydividing the determined quadrant. This means that there is a higherprobability that the information of the remaining two bits will bechanged during transportation. That is, of at least 3 bits included inone symbol, the bits determining a wider region have higher reliabilityand the bits determining a narrower region have lower reliability.

[0009] A transmitter of a common HSDPA (High-Speed Downlink PacketAccess) radio communication system is comprised of a channel encoder, aninterleaver and a modulator, as illustrated in FIG. 1.

[0010] Referring to FIG. 1, a tail bit generator 110 receives Ntransport blocks and adds associated tail bits to the respectivetransport blocks. A channel encoder 112 encodes the N tail bit-addedtransport blocks from the tail bit generator 110 and outputs codedsymbols. The channel encoder 112 has at least one coding rate in orderto encode the N transport blocks. The coding rate may be ½ or ¾. Whenthe channel encoder 112 supports a plurality of coding rates throughsymbol puncturing or symbol repetition using a ⅙ or ⅕ mother encoder, anoperation of selecting a coding rate from the available coding rates isrequired. In FIG. 1, the channel encoder 112 determines (selects) thecoding rate under the control of a controller 120.

[0011] A rate matcher 114 rate-matches the coded symbols from thechannel encoder 112. The rate matching is performed by repeating orpuncturing the coded symbols, when a transport channel is subject tomultiplexing or when the number of the output symbols of the channelencoder 112 is not identical to the number of symbols transported over aradio channel. An interleaver 116 interleaves the rate-matched codedsymbols from the rate matcher 114. The interleaving is performed tominimize a possible data loss during transportation. An M-ary modulator118 modulates the interleaved coded symbols by QPSK (Quadrature PhaseShift Keying), 8PSK (8-ary Phase Shift Keying), 16QAM or 64QAMmodulation. The controller 120 controls an operation of the channelencoder (or turbo encoder) 112 and a modulation mode of the modulator118 according to a current state of the radio channel. The HSDPA radiocommunication system uses AMCS (Adaptive Modulation and Coding Scheme)for the controller 120 in order to select the modulation modes (QPSK,8PSK, 16QAM and 64QAM) according to the radio environment. Though notillustrated in the drawing, the CDMA mobile communication system spreadstransport data using a Walsh code W and an orthogonal code PN, so that acorresponding mobile terminal (or UE (User Equipment)) can identify achannel and a base station (or Node B) transporting the data.

[0012] The structure of the transmitter has been described on theassumption that coded symbols are not divided into the systematic bitsand the parity bits. However, the coded symbols output from the channelencoder 112 of the transmitter can be divided into the systematic bitsand the parity bits. Of course, the systematic bits and the parity bitsoutput from the channel encoder 112 have different priorities. Namely,in the case where errors occur in the transport data at a given rate, itis possible to perform relatively correct decoding when the errors occurin the parity bits rather than in the systematic bits. The reason is, asstated above, because the systematic bits are actual data bits while theparity bits are supplemental bits added to correct errors occurredduring transportation in a decoding process.

[0013] However, the interleaver 116 of the conventional transmitter inthe communication system performs interleaving regardless of thepriorities of the systematic bits and the parity bits. That is, theconventional transmitter performs symbol mapping irrespective of thesystematic bits and the parity bits.

[0014] Hence, the conventional radio communication system has a higherror occurrence probability regardless of the priorities of thesystematic bits and the parity bits, when transporting data over thewireless network. Accordingly, there is a need for a technique capableof reducing a probability that errors will occur in the systematic bitshaving higher priority than the parity bits, thereby improving systemperformance.

SUMMARY OF THE INVENTION

[0015] It is, therefore, an object of the present invention to provide adata transportation/reception apparatus and method for improvingperformance of a radio communication system.

[0016] It is another object of the present invention to provide a datatransportation/reception apparatus and method having higher reliabilityin a radio communication system.

[0017] It is further another object of the present invention to providea data transportation/reception apparatus and method for receiving bitshaving higher priority at a receiver having a higher receptionprobability in a radio communication system.

[0018] It is yet another object of the present invention to provide adata transportation/reception apparatus and method for mapping data bitsto symbol bit positions having different reliabilities according topriorities of transport data bits.

[0019] It is still another object of the present invention to provide adata reception apparatus and method for receiving data bits mapped tosymbol bit positions having different reliabilities according topriorities of transport data bits.

[0020] It is still another object of the present invention to provide adata transportation apparatus and method for mapping data bits havinghigher priority to symbol bit positions having higher reliability, andmapping data bits having lower priority to symbol bit positions havinglower reliability.

[0021] It is still another object of the present invention to provide adata transportation apparatus and method for mapping systematic bits tosymbol bit positions having higher reliability and parity bits to symbolbit positions having lower reliability.

[0022] To achieve the above and other objects, the present inventionprovides a data transportation apparatus and method for dividingtransport data bits into bits having higher priority and bits havinglower priority, mapping the bits having higher priority to symbol bitpositions having higher reliability, and mapping the bits having lowerpriority to symbol bit positions having lower reliability.

[0023] Further, the present invention provides a data receptionapparatus and method for demodulating received modulated symbols,dividing the demodulated coded bits into two coded bit groups accordingto priority, deinterleaving the coded bit groups using differentdeinterleavers, and decoding the deinterleaved coded bits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of thepresent invention will become more apparent from the following detaileddescription when taken in conjunction with the accompanying drawings inwhich:

[0025]FIG. 1 illustrates a structure of a conventional transmitter in aCDMA communication system;

[0026]FIG. 2 illustrates a structure of a transmitter in a CDMA mobilecommunication system according to a first embodiment of the presentinvention;

[0027]FIG. 3 illustrates a structure of a receiver according to a firstembodiment of the present invention;

[0028]FIG. 4 illustrates a structure of a transmitter in a CDMA mobilecommunication system according to a second embodiment of the presentinvention;

[0029]FIG. 5 illustrates a structure of a transmitter in a CDMA mobilecommunication system according to a third embodiment of the presentinvention;

[0030]FIG. 6 illustrates an output format of the P/S converter in thetransmitter according to an embodiment of the present invention;

[0031]FIG. 7 illustrates simulation results obtained when the simulationis performed using 64QAM modulation according to an embodiment of thepresent invention; and

[0032]FIG. 8 illustrates simulation results obtained when the simulationis performed using 16QAM modulation according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0033] A preferred embodiment of the present invention will be describedherein below with reference to the accompanying drawings. In thefollowing description, well-known functions or constructions are notdescribed in detail since they would obscure the invention inunnecessary detail.

[0034] In the following description, it will be assumed that the channelencoder supports a coding rate of ½ and ¾, and the modulator supportsQPSK, 8PSK, 16QAM and 64QAM. Shown in Table 1 are available encodingoperations according to an embodiment of the present invention, when theassumption stated above is applied. TABLE 1 Coding Rate Modulation Mode½ QPSK 8PSK 16QAM 64QAM ¾ QPSK 8PSK 16QAM 64QAM

[0035] At the ½ coding rate (symmetric coding rate), the channel encoderoutputs 2 bits by receiving one input bit. One of the 2 output bits isan actual data bit, a systematic bit, while the remaining one bit is aparity bit for detecting and compensating for an error. However, at the¾ coding rate (asymmetric coding rate), the channel encoder outputs 4bits by receiving 3 input bits. The 4 output bits are divided into 3systematic bits and one parity bit.

[0036] A symbol pattern based on the 16QAM can be expressed as[H,H,L,L], and a symbol pattern based on the 64QAM can be expressed as[H,H,M,M,L,L]. In the symbol patterns, “H” represents a bit positionhaving High reliability, “L” represents a bit position having Lowreliability, and “M” represents a bit position having Mediumreliability. The present invention aims at mapping the bits havingrelatively higher priority (e.g., systematic bits and tail bits) to thebit positions having higher reliability, and mapping the bits havingrelative lower priority (e.g., parity bits and tail parity bits) to thebit positions having lower reliability, in performing symbol mapping onthe coded bits according to a predetermined symbol pattern.

[0037] Now, reference will be made to symbol mapping methods based onthe ½ and ¾ coding rates and the 16QAM and 64QAM modulations accordingto an embodiment of the present invention.

[0038] First, when using the ½ coding rate and the 16QAM modulation, thetransmitter maps 2 systematic bits to the 2 H-bit positions in thesymbol pattern, and maps 2 parity bits to the 2 L-bit positions in thesymbol pattern. In this case, it is preferable to use an interleaverwith a fixed length.

[0039] Second, when using the ¾ coding rate and the 16QAM modulation,the transmitter can use either an interleaver with a fixed length or aninterleaver with a variable length. When the interleaver with a fixedlength is used, the interleaver for interleaving systematic bits isidentical in length to the interleaver for interleaving parity bits.However, when the interleaver with a variable length is used, theinterleaver for interleaving systematic bits may not be identical inlength to the interleaver for interleaving parity bits.

[0040] When using the interleaver with a fixed length, the transmittermaps the first 2 systematic bits to the 2 H-bit positions in the symbolpattern after interleaving, and maps the remaining 1 systematic bit and1 parity bit to the 2 L-bit positions in the symbol pattern afterinterleaving. Therefore, when the interleaver has a fixed length, aseparate structure for matching the numbers of input bits to therespective interleavers is required. Although the description has beenmade of an example where the coded bits are subject to interleaving in aunit of 2 bits, this may be varied depending on a length of theinterleaver. That is, although the present invention will be describedwith reference to an example where the coded bits are subjected tointerleaving in a unit of 2 bits, it would be obvious to those skilledin the art that the coded bits may be subjected to interleaving in unitsof 4 or 8 bits.

[0041] However, when using the interleaver with a variable length, thetransmitter varies a length of the interleaver according to the numberof the systematic bits and the number of the parity bits. That is, thetransmitter interleaves 3 systematic bits and maps them to the 2 H-bitpositions and the 1 H-bit position in the symbol pattern. Further, thetransmitter maps 1 parity bit to the remaining 1 L-bit position in thesymbol pattern. Although the description has been made of an examplewhere the 2 systematic bits and the 1 parity bit are subject tointerleaving, the number of the bits subjected to interleaving may bevaried depending on a length of the interleaver. That is, when a lengthof the interleaver is 8, the coded bits may be subject to interleavingin a unit of 8 bits.

[0042] Third, when using the ½ coding rate and the 64 QAM modulation,the transmitter maps 2 systematic bits to the 2 H-bit positions in thesymbol pattern, and maps the remaining 1 systematic bit to the 1 M-bitposition in the symbol pattern. Further, the transmitter maps 2 paritybits to the 2 L-bit positions in the symbol pattern and maps theremaining 1 parity bit to the remaining 1 M-bit position in the symbolpattern. In this case, it is preferable to use an interleaver with afixed length.

[0043] Fourth, when using the ¾ coding rate and the 64QAM modulation,the transmitter may use either an interleaver with a fixed length or aninterleaver with a variable length. When using the interleaver with afixed length, transmitter determines a ratio of the systematic bits tothe parity bits such that as many systematic bits as possible may bemapped to the bit positions having higher reliability in the symbolpattern.

FIRST EMBODIMENT

[0044]FIG. 2 illustrates a structure of a transmitter in a CDMA mobilecommunication system according to a first embodiment of the presentinvention. Referring to FIG. 2, a channel encoder 210 receives transportdata and encodes the received transport data using a predetermined code.The predetermined code refers to a code for outputting transport bitsand error control bits of the transport bits, obtained by encoding thereceived data. For example, the transport bits are systematic bits (S),and the error control bits are parity bits (P). The predetermined codeincludes a turbo code and a systematic convolutional code, as mentionedabove.

[0045] A distributor 212 receives the systematic bits and the paritybits from the channel encoder 210, and distributes the systematic bitsand the parity bits to a plurality of interleavers. For example, whenthere exist two interleavers 214 and 216, the distributor 212distributes the systematic bits and the parity bits into two bit groupshaving the same number of bits. For example, when the ¾ coding rate andthe 16QAM modulation are used, the distributor 212 distributes the 2 Sbits to the first interleaver 214, and distributes the remaining 1 S bitand the 1 P bit to the second interleaver 216. As a result, one of twobit groups (or bit streams) is provided to the first interleaver 214,while the other bit group is provided to the second interleaver 216.However, when the transmitter uses a systematic coding rate such as ½coding rate, the distributor 212 is not essential in the firstembodiment. The reason is because when the ½ symmetric coding rate isused, the number of systematic bits is identical to the number of paritybits, and thus the systematic bits are provided to the first interleaver214 and the parity bits are provided to the second interleaver 216. Thedistributor 212 is also not essential even when the first and secondinterleavers 214 and 216 support a variable length, although they use anasymmetric coding rate such as ¾ coding rate. That is, the distributor212 is essential only when the first and second interleavers 214 and 216support the asymmetric coding rate and the fixed length.

[0046] The first and second interleavers 214 and 216 receive the codedbits from the distributor 212 or the channel encoder 210, and interleavethe received coded bits. The coded bits, may be the systematic bits, theparity bits, or a mixture of the systematic bits and the parity bits.When the received coded bits are the mixed bits of the systematic bitsand the parity bits, the distributor 212 is essential. In this case, aninterleaver receiving the mixture of the systematic bits and the paritybits rearrange the coded bits such that the systematic bits havinghigher priority always exist in specific positions, before interleaving.This assists the receiver in performing a decoding operation, and thespecific positions of the systematic bits are previously notified to thereceiver by the transmitter.

[0047] The sum of a length of the first interleaver 214 and a length ofthe second interleaver 216 are a value that can be divided by 2 (forQPSK), 3 (for 8PSK), 4 (for 16QAM) and 6 (for 64QAM). As an example ofthis condition, when the total length L_(tot) of the interleavers is 144bits, the following condition is satisfied.

L _(tot) =L _(sys) +L _(par)=144   (1)

[0048] where L_(sys) represents a length of the first interleaver andL_(par) represents a length of the second interleaver.

[0049] A parallel-to-serial (P/S) converter 218 receives in parallel theinterleaved coded bits output from the first interleaver 214 and theinterleaved coded bits output from the second interleaver 216, andoutputs the received coded bits in series. For example, when the codedbits having the higher priority are interleaved by the first interleaver214 and the coded bits having the lower priority are interleaved by thesecond interleaver 216, the P/S converter 218 first outputs the codedbits received from the first interleaver 214 and then outputs the codedbits received from the second interleaver 216. This is to map thesystematic bits having the higher priority to the bit positions havingthe higher reliability in a succeeding modulation process. An outputformat of the P/S converter 218 is illustrated in FIG. 6. In FIG. 6, “HParts” represent the bits having higher priority, while “L Parts”represent the bits having lower priority. The H parts and the L partsare symmetrical for the interleaver with a fixed length, andasymmetrical for the interleaver with a variable length.

[0050] A modulator 220 symbol-maps the coded bits from the P/S converter218 according to a predetermined symbol pattern, and transports thesymbol-mapped coded bits to the receiver. For example, when themodulator 220 uses the 16QAM modulation, the coded bits are subject tosymbol mapping according to the symbol pattern [H,H,L,L]. However, whenthe modulator 220 uses the 64QAM modulation, the coded bits are subjectto symbol mapping according to the symbol pattern [H,H,M,M,L,L].

[0051] Though not illustrated in FIG. 2, a transmitter in the CDMAmobile communication system may further include a rate matcher forperforming rate matching by repeating and puncturing the coded bits fromthe channel encoder 210.

[0052]FIG. 3 illustrates a structure of a receiver according to a firstembodiment of the present invention. The receiver corresponds to thetransmitter of FIG. 2. Referring to FIG. 3, a demodulator 310 receivesdata transported from the transmitter, and demodulates the received dataaccording to a demodulation mode corresponding to the modulation modeused by the modulator 220 of the transmitter.

[0053] A serial-to-parallel (S/P) converter 312 receives in series thedemodulated coded bits from the demodulator 310, and outputs in parallelthe received coded bits by switching. For example, when the modulator220 in the transmitter uses the 16QAM modulation, the S/P converter 312outputs first 2 bits to a first deinterleaver 314 and the next 2 bits toa second deinterleaver 316, by switching the coded bits in a 2-bit unit.When the modulator 220 in the transmitter uses the 64QAM modulation, theS/P converter 312 outputs first 3 bits to the first deinterleaver 314and the next 3 bits to the second deinterleaver 316, by switching thecoded bits in a 3-bit unit. However, when the transmitter uses anasymmetric coding rate and interleavers having a variable length, theS/P converter 312 recognizes the variable length based on previouslyreceived information. In this manner, the S/P converter 312 outputs asmany coded bits as a length of the first interleaver 214 in thetransmitter to the first deinterleaver 314, and outputs as many codedbits as a length of the second interleaver 216 in the transmitter to thesecond deinterleaver 316.

[0054] The first and second deinterleavers 314 and 316 deinterleave thecoded bits provided from the S/P converter 312. Operations of the firstand second deinterleavers 314 and 316 correspond to operations of thefirst and second interleavers 214 and 216 in the transmitter. That is,since the first and second deinterleavers 314 and 316 (based on a priorstorage and/or exchange of information) recognize the interleavingpatterns performed by the first and second interleavers 214 and 216 ofthe transmitter, the same interleaving pattern is pre-arranged for thetransmitter and the receiver. For example, the transmitter maypreviously inform the receiver of the interleaving pattern informationas system information before call setup.

[0055] A classifier 318 classifies the deinterleaved coded bits providedfrom the first and second deinterleavers 314 and 316. The coded bits maybe systematic bits, parity bits or a mixture of the systematic bits andthe parity bits. When the coded bits are the mixed bits of thesystematic bits and the parity bits, the classifier 318 is an essentialelement. In this case, among the coded bits output from a deinterleaverfor deinterleaving the mixed bits of the systematic bits and the paritybits, the systematic bits having higher priority will always exist inspecific positions. By prior arrangement, the transmitter and thereceiver will agree on the positions of the systematic bits, analogousto the interleaving pattern information. For example, the transmittermay previously inform the receiver of the systematic bit positioninformation as system information. For example, when the coded bitshaving higher priority are deinterleaved by the first deinterleaver 314and the coded bits having lower priority are deinterleaved by the seconddeinterleaver 316, the classifier 318 may first output the deinterleavedcoded bits from the first deinterleaver 314 and then output thedeinterleaved coded bits from the second deinterleaver 316. However, theclassifier 318 is not an essential element when the transmitter uses thesymmetric coding rate such as ½ coding rate.

[0056] A channel decoder 320 receives the coded bits from the classifier318 or the coded bits from the first and second deinterleavers 314 and316, and decodes the received coded bits according to a predetermineddecoding method, thereby outputting desired decoded bits. For thepredetermined decoding method, a method for receiving systematic bitsand parity bits and then decoding the systematic bits is used, and thedecoding method is determined based on the encoding method of thetransmitter.

[0057] Operations of the first embodiment of the present invention willbe described in detail herein below with reference to FIGS. 2 and 3.

[0058] First, operations of the transmitter will be described in detailwith reference to FIG. 2. Operations of the transmitter according to thefirst embodiment of the present invention can be divided into threeoperations depending on the coding rate and whether the transmitter usesinterleavers with a fixed length or interleavers with a variable length.The three operations include (1) a first operation where the transmitteruses the symmetric coding rate, (2) a second operation where thetransmitter uses the asymmetric coding rate and the interleavers with afixed length, and (3) a third operation where the transmitter uses theasymmetric coding rate and the interleavers with a variable length. Adetailed description of the three operations according to the firstembodiment of the present invention will be given below.

First Operation (Transmitter)

[0059] An operation of the transmitter using the symmetric coding ratewill be described in detail below. Transport data is provided to thechannel encoder 210 where it is encoded by a specific code. That is, thechannel encoder 210 outputs systematic bits (S bits), which are actualtransport data, and parity bits (P bits) for error controlling of thetransport data, through encoding. For example, when the channel encoder210 uses the symmetric coding rate such as ½ coding rate, it outputs theS bits and the P bits in the same ratio. The S bits provided from thechannel encoder 210 are provided to the first interleaver 214, while theP bits provided from the channel encoder 210 are provided to the secondinterleaver 216.

[0060] Therefore, the S bits are interleaved by the first interleaver214 and the P bits are interleaved by the second interleaver 216. Theinterleaving pattern of the first and second interleavers 214 and 216 ispreviously determined, and by pre-arrangement the determinedinterleaving pattern is recognized by the receiver.

[0061] The interleaved S and P bits from the first and secondinterleavers 214 and 216 are provided in parallel to the P/S converter218. The interleaved S bits and P bits provided in parallel to the P/Sconverter 218 are output in series. Preferably, the P/S converter 218first outputs a predetermined number of the interleaved S bits and thenoutputs a predetermined number of the interleaved P bits.

[0062] The interleaved S and P bits from the P/S converter 218 areprovided to the modulator 220 where they are subject to symbol mappingaccording to the predetermined symbol pattern and then transmitted tothe receiver of FIG. 3. For example, when the modulation mode of themodulator 220 is 16QAM, the predetermined symbol pattern is defined as[H,H,L,L]. Therefore, the modulator 220 maps the 2 interleaved S bits tothe H-bit positions in the symbol pattern and the 2 interleaved P bitsto the L-bit positions in the symbol pattern, and then the symbol-mappedbits are transmitted to the receiver. However, when the modulation modeof the modulator 220 is 64QAM, the predetermined symbol pattern isdefined as [H,H,M,M,L,L]. Therefore, the modulator 220 maps 3interleaved S bits to 2 H-bit positions and 1 M-bit position in thesymbol pattern, and maps 3 interleaved P bits to the remaining 1 M-bitposition and 2 L-bit positions in the symbol pattern. The symbol-mappedbits are then transmitted to the receiver.

First Operation (Receiver)

[0063] An operation of the receiver using the symmetric coding rate willbe described in detail below. Data received from the transmitter isprovided to the demodulator 310 where the received data is demodulatedin coded bits according to a demodulation mode corresponding to themodulation mode used by the modulator 220 of the transmitter. Thedemodulated coded bits from the demodulator 310 are provided in seriesto the S/P converter 312, and the S/P converter 312 outputs the receivedcoded bits in parallel. For example, when the modulator 220 of thetransmitter uses 16QAM modulation, the S/P converter 312 outputs thefirst 2 bits to the first deinterleaver 314 and the next 2 bits to thesecond deinterleaver 316. However, when the modulator 220 of thetransmitter uses 64QAM modulation, the S/P converter 312 outputs thefirst 3 bits to the first deinterleaver 314 and the next 3 bits to thesecond deinterleaver 316.

[0064] The coded bits from the S/P converter 312 are classified into twobit groups, and the classified bit groups are provided to the first andsecond deinterleavers 314 and 316, where the bit groups are subject todeinterleaving. The deinterleaving operations of the first and seconddeinterleavers 314 and 316 correspond to the interleaving operationsperformed by the first and second interleavers 214 and 216 of thetransmitter. That is, the first and second deinterleavers 314 and 316perform deinterleaving according to the interleaving pattern performedby the first and second interleavers 214 and 216 of the transmitter.

[0065] The deinterleaved coded bits from the first and seconddeinterleavers 314 and 316 are provided to the decoder 320 where thecoded bits are decoded into desired received bits according to apredetermined decoding method. For the predetermined decoding method, amethod for receiving S bits and P bits and then decoding the S bits isused, and the decoding method is determined based on the encoding methodof the transmitter.

Second Operation (Transmitter)

[0066] An operation of the transmitter using the asymmetric coding rateand the interleavers with a fixed length will be described in detailbelow. Transport data is provided to the channel encoder 210 where it isencoded by a specific code. That is, the channel encoder 210 outputssystematic bits (S bits), which are actual transport data, and paritybits (P bits) for error controlling of the transport data, throughencoding. For example, when the channel encoder 210 uses the asymmetriccoding rate such as ¾ coding rate, it outputs the S bits and the P bitsin a ratio based on the ¾ coding rate. That is, the channel encoder 210outputs 3 S bits and 1 P bit.

[0067] The S bits and the P bits from the channel encoder 210 areprovided to the distributor 212 where they are divided into two bitgroups in the same ratio. That is, when 16QAM modulation is used, thedistributor 212 provides 2 S bits to the first interleaver 214, andprovides the remaining 1 S bit and 1 P bit to the second interleaver216.

[0068] A description will be made as to how the distributor 212 operatesin two possible cases. In a first case where the number of thesystematic bits is larger than the number of the parity bits, thedistributor 212 fills the first interleaver 214 with the systematicbits, and fills the second interleaver 216 with the remaining systematicbits along with the parity bits. In a second case where the number ofthe systematic bits is less than the number of the parity bits, thedistributor 212 fills the first interleaver 214 with the systematicbits, fills the remaining part of the first interleaver 214 with paritybits, and fills the second interleaver 216 with the remaining paritybits.

[0069] Therefore, the 2 S bits are interleaved by the first interleaver214, and the remaining 1 S bit and the 1 P bit are interleaved by thesecond interleaver 216. The interleaving pattern of the first and secondinterleavers 214 and 216 is previously set, and the same interleavingpattern is previously set in the receiver. Further, provided with the Sbit and the P bit from the distributor 212, the second interleaver 216determines the S bit position before interleaving based on a previouslydetermined pattern that is the same as the receiver, so that thereceiver can efficiently classify the S bit and the P bit in thedecoding process. For example, the S bit to be interleaved by the secondinterleaver 216 is located in a front position before interleaving, sothat the receiver can estimate a bit located in the front position asthe S bit after deinterleaving.

[0070] The S bits interleaved by the first interleaver 214, and the Sbit and the P bit interleaved by the second interleaver 216 are providedin parallel to the P/S converter 218. The P/S converter 218 outputs inseries the provided interleaved S bits and P bit and the providedinterleaved S bit and P bit. Preferably, the P/S converter 218 firstoutputs the output bits of the first interleaver 214 and then outputsthe output bits of the second interleaver 216.

[0071] The interleaved S bits and the interleaved S bit and P bit fromthe P/S converter 218 are provided to the modulator 220 where they aresubject to symbol mapping according to the predetermined symbol patternand then are transmitted to the receiver of FIG. 3. For example, whenthe modulation mode of the modulator 220 is 16QAM, the predeterminedsymbol pattern is defined as [H,H,L,L]. Therefore, the modulator 220maps the 2 interleaved S bits to the H-bit positions in the symbolpattern and the 2 interleaved bits of the S bit and the P bit to theL-bit positions in the symbol pattern, and the symbol-mapped bits arethen transmitted to the receiver. However, when the modulation mode ofthe modulator 220 is 64QAM, the predetermined symbol pattern is definedas [H,H,M,M,L,L]. Therefore, the modulator 220 maps 3 S bits interleavedby the first interleaver 214 to 2 H-bit positions and 1 M-bit positionin the symbol pattern, and maps 3 P bits interleaved by the secondinterleaver 216 to the remaining 1 M-bit position and 2 L-bit positionsin the symbol pattern. The symbol-mapped bits are then transmitted tothe receiver.

[0072] In this case, since the two interleavers have a fixed size, it isnot necessary to vary the length of the interleavers according to thecoding rate. Thus, it is simple to implement the interleavers. However,when there exist three or more reliability levels as in the high ordermodulation of over 64QAM, there is a case where an optimal condition isnot satisfied. The “optimal condition” refers to a condition in whichthe bits having higher priority are always mapped to the bit positionshaving higher reliability. In the optimal condition, if the number ofthe S bits is larger than the number of P bits, the remaining S isprovided to the second interleaver and then interleaved along with the Pbit. Accordingly, though the S bits interleaved by the first interleaver214 are mapped to the bit positions having the higher reliability, the Sbit provided to the second interleaver 216 may be mapped to the bitposition having lower reliability. To avoid this, it is possible toincrease the number of interleavers to cover the 3 different reliabilitylevels. Increasing the number of the interleavers is mere extension ofthe present invention, so the detailed description will not be given inorder not to obscure the gist of the present invention. However, eventhe transmitter using the two interleavers with a fixed lengthdemonstrates better performance than the conventional transmitter.

Second Operation (Receiver)

[0073] An operation of the receiver using the asymmetric coding rate andthe interleavers with a fixed length will be described in detail below.Data received from the transmitter is provided to the demodulator 310where the received data is demodulated in coded bits according to ademodulation mode corresponding to the modulation mode used by themodulator 220 of the transmitter. The demodulated coded bits from thedemodulator 310 are provided in series to the S/P converter 312, and theS/P converter 312 outputs the received coded bits in parallel. Forexample, when the modulator 220 of the transmitter uses 16QAMmodulation, the S/P converter 312 outputs the first 2 bits to the firstdeinterleaver 314 and the next 2 bits to the second deinterleaver 316.In this case, the first 2 bits are comprised of only the systematicbits, and the next 2 bits are comprised of an S bit and a P bit.However, when the modulator 220 of the transmitter uses 64QAMmodulation, the S/P converter 312 outputs the first 3 bits to the firstdeinterleaver 314 and the next 3 bits to the second deinterleaver 316.

[0074] The coded bits from the S/P converter 312 are classified into twobit groups, and the classified bit groups are provided to the first andsecond deinterleavers 314 and 316, where the bit groups are subject todeinterleaving. The deinterleaving operations of the first and seconddeinterleavers 314 and 316 correspond to the interleaving operationsperformed by the first and second interleavers 214 and 216 of thetransmitter. That is, the first and second deinterleavers 314 and 316perform deinterleaving according to the interleaving pattern performedby the first and second interleavers 214 and 216 of the transmitter.

[0075] The deinterleaved coded bits from the first and seconddeinterleavers 314 and 316 are provided to the classifier 318 where thecoded bits are classified into the S bits and the P bits. As the outputbits of the second deinterleaver 316 are mixed bits of the S bit and theP bits, by pre-arrangement along with the transmitter, the classifier318 recognizes the position where the S bit among the deinterleaved bitsexists.

[0076] The coded bits from the classifier 318 are provided to thedecoder 320 where the coded bits are decoded into desired received bitsaccording to a predetermined decoding method. For the predetermineddecoding method, a method for receiving S bits and P bits and thendecoding the S bits is used. The decoding method is determined based onthe encoding method of the transmitter.

Third Operation (Transmitter)

[0077] An operation of the transmitter using the asymmetric coding rateand the interleavers with a variable length will be described in detailbelow. Transport data is provided to the channel encoder 210 where it isencoded by a specific code. That is, the channel encoder 210 outputssystematic bits (S bits), which are actual transport data, and paritybits (P bits) for error controlling of the transport data, throughencoding. In this example, when the channel encoder 210 uses theasymmetric coding rate such as ¾ coding rate, it outputs the S bits andthe P bits in a different ratio based on the ¾ coding rate. That is, thechannel encoder 210 outputs 3 S bits and 1 P bit. The S bits from thechannel encoder 210 are provided to the first interleaver 214, and the Pbits from the channel encoder 210 are provided to the second interleaver216.

[0078] Therefore, the S bits are interleaved by the first interleaver214, and the P bits are interleaved by the second interleaver 216. Theinterleaving pattern and length of the first and second interleavers 214and 216 are previously determined, and the determined interleavingpattern and length are by pre-arrangement also recognized by thereceiver. The length can be determined based on a ratio of the S bits tothe P bits.

[0079] The interleaved S bits and P bits from the first and secondinterleavers 214 and 216 are provided in parallel to the P/S converter218. The P/S converter 218 outputs the provided interleaved S bits and Pbits in series. Preferably, the P/S converter 218 outputs theinterleaved S bits and P bits such that the interleaved S bits aremapped to the bit positions having higher reliability.

[0080] The interleaved S bits and the interleaved P bits from the P/Sconverter 218 are provided to the modulator 220 where they are mapped topredetermined bit positions and then transmitted to the receiver of FIG.3. For example, when a length of the first interleaver 214 receiving theS bits is 18 bits long and a length of the second interleaver 216receiving the P bits is 6 bits long, a symbol mapping operationperformed by the modulator 220 is as follows.

[0081] First, when the modulation mode of the modulator 220 is 16QAM,the predetermined symbol pattern is defined as [H,H,L,L]. Therefore, themodulator 220 maps the 2 interleaved S bits to the H-bit positions inthe symbol pattern, maps the remaining 1 S bit and 1 P bit to the L-bitpositions in the symbol pattern, and then transmits the symbol-mappedbits to the receiver.

[0082] Next, when the modulation mode of the modulator 220 is 64QAM, thepredetermined symbol pattern is defined as [H,H,M,M,L,L]. Therefore, ina first modulation process, the modulator 220 symbol-maps the S bits andthe P bits according to the symbol pattern in a ratio of 4:2. In asecond modulation process, the modulator 220 symbol-maps the S bits andthe P bits according to the symbol pattern in a ratio of 5:1. In a thirdmodulation process, the modulator 220 symbol-maps the S bits and the Pbits according to the symbol pattern in a ratio of 4:2. In a fourthmodulation process, the modulator 220 symbol-maps the S bits and the Pbits according to the symbol pattern in a ratio of 5:1. That is, in thefirst and third modulation processes where the ratio of the S bits tothe P bits is 4:2, the modulator 220 maps the 2 S bits to the 2 H-bitpositions in the symbol pattern, maps the remaining 2 S bits to the 2M-bit positions in the symbol pattern, and maps the 2 P bits to the 2L-bit positions in the symbol pattern. The symbol-mapped bits are thentransmitted to the receiver. In the second and fourth modulationprocesses where the ratio of the S bits to the P bits is 5:1, themodulator 220 maps the 2 S bits to the 2 H-bit positions in the symbolpattern, maps the remaining 2 S bits to the 2 M-bit positions in thesymbol pattern, and maps the last 1 S bit and the 1 P bit to the 2 L-bitpositions in the symbol pattern. The symbol-mapped bits are thentransmitted to the receiver.

[0083] Shown in Table 2 are the modulation processes performed by thetransmitter using the asymmetric coding rate and the 64QAM modulation.TABLE 2 H H M M L L 1^(st) Modulation S S S S P P 2^(nd) Modulation S SS S S P 3^(rd) Modulation S S S S P P 4^(th) Modulation S S S S S P

[0084] When the length of the interleavers is varied as described above,it is necessary to disadvantageously control the size (length) of thetwo interleavers according to the coding rate. It is nonethelesspossible to perform symbol mapping in an optimal condition regardless ofthe coding rate and the order of the modulator. In addition, since it isnot necessary to distribute the S bits and the P bits to the twointerleavers in a specific ratio, the transmitter does not require thedistributor 212.

Third Operation (Receiver)

[0085] An operation of the receiver using the asymmetric coding rate andthe interleavers with a variable length will be described in detailbelow. Data received from the transmitter is provided to the demodulator310 where the received data is demodulated in coded bits according to ademodulation mode corresponding to the modulation mode used by themodulator 220 of the transmitter. The demodulated coded bits from thedemodulator 310 are provided in series to the S/P converter 312, and theS/P converter 312 outputs the received coded bits in parallel. When thetransmitter uses the asymmetric coding rate and the interleavers with avariable length, the S/P converter 312 by pre-arrangement will recognizethe varying length. Thus, the S/P converter 312 outputs as many codedbits as a length of the first interleaver 214 in the transmitter to thefirst deinterleaver 314, and outputs as many coded bits as a length ofthe second interleaver 216 in the transmitter to the seconddeinterleaver 316.

[0086] When the modulator 220 of the transmitter uses 16QAM modulation,the S/P converter 312 outputs the first 3 bits to the firstdeinterleaver 314 and the next 1 bits to the second deinterleaver 316.However, when the modulator 220 of the transmitter uses 64QAMmodulation, the S/P converter 312 divides the coded bits from thedemodulator 310 into a series output of S bits and P bits according to aratio of the S bits and the P bits used by the P/S converter 218 of thetransmitter. The ratio can be determined based on a ratio of a length ofthe first interleaver 214 to a length of the second interleaver 216 ofthe transmitter.

[0087] For example, when the P/S converter 218 of the transmitter hasused 4:2, 5:1, 4:2, and 5:1 ratios of the S bits to the P bits, i.e.,ratios of the length of the first interleaver 214 to the length of thesecond interleaver 216, the S/P converter 312 outputs the first 4 bitsto the first deinterleaver 314 and the next 2 bits to the seconddeinterleaver 316, in first and third processes. In second and fourthprocesses, the S/P converter 312 outputs the first 5 bits to the firstdeinterleaver 314 and the next 1 bit to the second deinterleaver 316.

[0088] The coded bits from the S/P converter 312 are classified into twobit groups, and the classified bit groups are provided to the first andsecond deinterleavers 314 and 316, where the bit groups are subject todeinterleaving. The deinterleaving operations of the first and seconddeinterleavers 314 and 316 correspond to the interleaving operationsperformed by the first and second interleavers 214 and 216 of thetransmitter. That is, the first and second deinterleavers 314 and 316perform deinterleaving according to the interleaving pattern performedby the first and second interleavers 214 and 216 of the transmitter.

[0089] The deinterleaved coded bits from the first and seconddeinterleavers 314 and 316, previously divided into the S bits and the Pbits by the S/P converter 312, are provided to the decoder 320 where thecoded bits are decoded into desired received bits according to apredetermined decoding method. For the predetermined decoding method, amethod for receiving S bits and P bits and then decoding the S bits isused. The decoding method is determined based on the encoding method ofthe transmitter.

SECOND EMBODIMENT

[0090]FIG. 4 illustrates a structure of a transmitter in an HSDPA mobilecommunication system according to a second embodiment of the presentinvention. Referring to FIG. 4, a tail bit generator 410 receivestransport data, and adds associated tail bits to the received transportdata. A channel encoder 412, under the control of a controller 426,encodes the tail bits-added data received from the tail bit generator410 using a predetermined code. The predetermined code refers to a codefor outputting transport bits and error control bits of the transportbits. For example, the transport bits are systematic bits (S), and theerror control bits are parity bits (P). The predetermined code includesa turbo code and a systematic convolutional code, as mentioned above.

[0091] A rate matcher 414 performs rate matching by repeating andpuncturing the coded bits from the channel encoder 412. A distributor416, under the control of the controller 426, receives the systematicbits and the parity bits from the rate matcher 414, and distributes thesystematic bits and the parity bits to a plurality of interleavers.

[0092] First and second interleavers 418 and 420 receive the coded bitsfrom the distributor 416, and interleave the received coded bits. Thecoded bits may be the systematic bits, the parity bits, or a mixture ofthe systematic bits and the parity bits. When the received coded bitsare the mixed bits of the systematic bits and the parity bits, thedistributor 416 is essential. In this case, an interleaver receiving themixed bits of the systematic bits and the parity bits rearranges thecoded bits such that the systematic bits having higher priority alwaysexist in specific positions, before interleaving. This assists thereceiver in performing a decoding operation, and the transmitterpre-notifies the receiver of the specific positions of the systematicbits. When the first and second interleavers 418 and 420 have a variablelength, they are controlled by the controller 426. That is, when thefirst and second interleavers 418 and 420 have a variable length, thelengths of the first and second interleavers 418 and 420 are determinedby the controller 426.

[0093] A parallel-to-serial (P/S) converter 422, under the control ofthe controller 426, receives in parallel the interleaved coded bitsoutput from the first interleaver 418 and the interleaved coded bitsoutput from the second interleaver 420, and outputs the received codedbits in series. For example, when the coded bits having the higherpriority are interleaved by the first interleaver 418 and the coded bitshaving the lower priority are interleaved by the second interleaver 420,the P/S converter 422 first outputs the coded bits received from thefirst interleaver 418 and then outputs the coded bits received from thesecond interleaver 420. This is to map the systematic bits having thehigher priority to the bit positions having the higher reliability in asucceeding modulation process.

[0094] A modulator 424 symbol-maps the coded bits from the P/S converter422 according to a predetermined symbol pattern, and then thesymbol-mapped coded bits are transmitted to the receiver. For example,when the modulator 424 uses the 16QAM modulation, the coded bits aresubject to symbol mapping according to a symbol pattern [H,H,L,L].However, when the modulator 424 uses the 64QAM modulation, the codedbits are subject to symbol mapping according to a symbol pattern[H,H,M,M,L,L].

[0095] The controller 426 controls the overall operation of thetransmitter according to the second embodiment of the present invention.First, the controller 426 determines a coding rate and a modulation modeto be used in the current radio channel state. The controller 426controls the coding rate of the channel encoder (or turbo encoder) 412based on the determined coding rate to be used, and controls themodulator 424 based on the determined modulation mode. In addition, thecontroller 426 controls a distribution pattern of the distributor 416based on the determined coding rate and the determined modulation mode.For example, when the plurality of interleavers include the twointerleavers 418 and 420, the controller 426 controls the distributor416 to distribute the systematic bits and the parity bits into two bitgroups (bit streams) having the same number of bits. One of the two bitgroups is provided to the first interleaver 418, and the other bit groupis provided to the second interleaver 420. If the plurality ofinterleavers include 3 interleavers, the controller 426 controls thedistributor 416 to distribute the systematic bits and the parity bitsinto three bit groups. However, when the transmitter uses the symmetriccoding rate such as ½ coding rate, the distributor 416 is not essentialin this embodiment. The reason is because when the ½ symmetric codingrate is used, the number of systematic bits is identical to the numberof parity bits, and thus the systematic bits are provided to the firstinterleaver 418 and the parity bits are provided to the secondinterleaver 420. This is equally applied even when the first and secondinterleavers 418 and 420 support a variable length, although they use anasymmetric coding rate such as ¾ coding rate. That is, the distributor416 is essential only when the first and second interleavers 418 and 420support the asymmetric coding rate and the fixed length.

THIRD EMBODIMENT

[0096]FIG. 5 illustrates a structure of a transmitter in a CDMA mobilecommunication system according to a third embodiment of the presentinvention. The transmitter of FIG. 5 outputs coded symbols in series byan interleaver without a separate P/S converter.

[0097] Referring to FIG. 5, transport data is provided to a channelencoder 510 where the received transport data is encoded by apredetermined code. That is, the channel encoder 510 outputs systematicbits (S bits), which are actual transport data, and parity bits (P bits)for error controlling of the transport data. The S bits and the P bitsfrom the channel encoder 510 are provided to a controller 514 that ispart of an interleaver 512. The controller 514 assigns a predeterminedaddress to the S bits provided from the channel encoder 510, andsequentially stores the S bits in an S region of a memory 516. Inaddition, the controller 514 assigns a predetermined address to the Pbits provided from the channel encoder 510, and sequentially stores theP bits in a P region of the memory 516.

[0098] Further, the controller 514 performs a control operation oftransporting the S bits and the P bits stored in the memory 516.Specifically, the controller 514 analyzes the coding rate used by thechannel encoder 510 to transmit the S bits and the P bits stored in thememory 516, and also analyzes the modulation mode to be used by amodulator 518. After determining the coding rate and the modulation modethrough the analysis, the controller 514 reads the S bits and the P bitsstored in the memory 516 based on the determined coding rate andmodulation mode.

[0099] For example, when the determined coding rate is a symmetriccoding rate ½ and the determined modulation mode is 16QAM or 64QAM, thecontroller 514 repeatedly alternately accesses the S region and the Pregion of the memory 516 in the same ratio, and outputs the same numberof the S bits and the P bits. That is, the controller 514 first reads 2(or 3) S bits by accessing the S region, and then reads 2 (or 3) P bitsby accessing the P region. In the case of 2 bits, the 2 S bits and the 2P bits output from the controller 514 are provided to the modulator 518where the S bits and the P bits are subject to 16QAM modulation.Specifically, the 2 S bits are mapped to the 2 H-bit positions in thesymbol pattern [H,H,L,L] defined for the 16QAM modulation, and the 2 Pbits are mapped to the 2 L-bit positions in the symbol pattern.

[0100] However, when the determined coding rate is a ¾ asymmetric codingrate and the determined modulation mode is 16QAM, the controller 514outputs the S bits and the P bits in a ratio of 3:1 by accessing the Pregion of the memory 516 once while accessing the S region 3 times. Inthis case, the 3 S bits and the 1 P bit output from the controller 514are provided to the modulator 518 where the S bits and the P bit aresubject to 16QAM modulation. Specifically, the 2 S bits are mapped tothe 2 H-bit positions in the symbol pattern [H,H,L,L] defined for the16QAM modulation, and the remaining 1 S bit and the 1 P bit are mappedto the 2 L-bit positions in the symbol pattern.

[0101] Finally, when the determined coding rate is the ¾ asymmetriccoding rate and the determined modulation mode is 64QAM, the controller514 outputs the S bits and the P bits by accessing the S region and theP region of the memory 516 in a predetermined ratio. Here, the totalaccess number of the memory 516 is a value that can be divided by 2 (forQPSK), 3 (for 8PSK), 4 (for 16QAM) and 6 (for 64QAM). As an example ofthis condition, when the total access number A_(tot) is 144 bits, thefollowing condition is satisfied.

A _(tot) =A _(sys) +A _(par)=144   (2)

[0102] where A_(sys) represents the number of accesses to the S regionand A_(par) represents the number of accesses to the P region.

[0103] In the 64QAM modulation mode, since one symbol is comprised of 6bits and A_(sys):A_(par)=3:1, 9 S bits and 3 P bits are required inconstructing 2 symbols (12 bits). That is, the controller 514 shouldtheoretically output 4.5 S bits and 1.5 P bits per symbol. However,because the bit numbers are not an integer, the controller 514 changesthe number of output bits in a symbol unit. For example, the controller514 first outputs 4 S bits and 2 P bits, and then outputs 5 S bits and 1P bit.

[0104] In this case, the S bits and the P bits output from thecontroller 514 are provided to the modulator 518, where the providedbits are subject to 64QAM modulation. When the 4 S bits and the 2 P bitsare provided from the controller 514, the modulator 518 maps the first 2S bits to the 2 H-bit positions in the symbol pattern [H,H,M,M,L,L]defined for the 64QAM modulation, maps the remaining 2 S bits to the 2M-bit positions in the symbol pattern, and maps the 2 P bits to the 2L-bit positions in the symbol pattern. Meanwhile, when the 5 S bits andthe 1 P bit are provided from the controller 514, the modulator 518 mapsthe first 2 S bits to the 2 H-bit positions in the symbol pattern[H,H,M,M,L,L] defined for the 64QAM modulation, maps the next 2 S bitsto the 2 M-bit positions in the symbol pattern, and maps the remaining 1S bit and the 1 P bit to the 2 L-bit positions in the symbol pattern.

[0105]FIG. 7 illustrates simulation results obtained when the simulationis performed using an encoder and a decoder both supporting 64QAMmodulation according to an embodiment of the present invention. FIG. 8illustrates simulation results obtained when the simulation is performedusing an encoder and a decoder both supporting 16QAM modulationaccording to an embodiment of the present invention. FIGS. 7 and 8 provethe effects of the invention. While the simulations were performed in acontrolled setting, they are sufficient to show the beneficial effectsof the invention. The simulation results of FIGS. 7 and 8 show acomparison between a bit error rate (BER) and a bit-to-noise ratio(E_(b)/N_(o)). According to the simulation results, the invention showsan increase in a gain of about 0.4 dB or over for both the 16QAM and the64QAM as compared with the prior art. The simulation results of FIGS. 7and 8 were obtained in the simulation condition where AWGN (AdditiveWhite Gaussian Noise) exists, turbo encoder input block size of 24,3043bits, coding rate of ½, and the interleavers with a fixed length areused.

[0106] As described above, the present invention maps the bits havinghigher priority to the bit positions having higher reliability, therebyobtaining superior transportation efficiency in the technical fields oferror control coding, modulation/demodulation and data transportation.Further, the invention can be applied not only to the transceiver of theexisting wired/wireless communication system, but also to thetransceiver of the 3^(rd) generation mobile communication system,IMT-2000 system, thus improving the overall system performance. This isachieved by modulating (mapping) the bits having higher priority withthe bits having higher reliability, which are less affected by thenoises and environments. That is, compared with the conventional system,the system according to the present invention has a lower bit error rate(BER) and improved system performance.

[0107] While the invention has been shown and described with referenceto a certain preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A method for processing data comprised of bitshaving higher priority and bits having relatively lower priority,generated by an encoder, using a high-order modulator in which a bitstream is generated comprised of at least 3 bits represents one symboland the bit stream is comprised of a first bit part having higherreliability and a second bit part having relatively lower reliability,comprising the steps of: dividing output bits of the encoder into bitshaving higher priority and bits having relatively lower priority; andmodulating the bits having higher priority and the bits havingrelatively lower priority such that the divided bits having higherpriority are situated in the first bit part and the divided bits havingrelatively lower priority are situated in the second bit part.
 2. Themethod as claimed in claim 1, wherein the dividing step comprises thestep of distributing the bits having higher priority and the bits havingrelatively lower priority based on a ratio of the bits having higherpriority to the bits having relatively lower priority, such that thebits having the higher priority are equal in number to the bits havingrelatively lower priority.
 3. The method as claimed in claim 1, whereinthe dividing step comprises the step of first outputting the bits havinghigher priority and succeedingly outputting the bits having relativelylower priority.
 4. The method as claimed in claim 1, wherein the bitshaving higher priority are systematic bits.
 5. The method as claimed inclaim 4, wherein the bits having relatively lower priority are paritybits.
 6. The method as claimed in claim 2, wherein the ratio of the bitshaving higher priority to the bits having relatively lower priority is½, which is a coding rate of the encoder.
 7. The method as claimed inclaim 2, wherein the ratio of the bits having higher priority to thebits having relatively lower priority is ¾, which is a coding rate ofthe encoder.
 8. The method as claimed in claim 1, further comprising thestep of determining the number of bit streams mapped to the one symbolaccording to a modulation mode based on a radio channel state.
 9. A dataprocessing apparatus in a mobile communication system, for processingdata comprised of bits having higher priority and bits having relativelylower priority, generated by an encoder at a predetermined coding rate,comprising: a first interleaver for interleaving the bits having higherpriority; a second interleaver for interleaving the bits havingrelatively lower priority; and a modulator for mapping output bits ofthe first interleaver to a first bit part and output bits of the secondinterleaver to a second bit part thus creating a bit stream comprised ofat least 3 bits to one symbol, the bit stream being comprised of thefirst bit part having higher reliability and the second bit part havingrelatively lower reliability.
 10. The apparatus as claimed in claim 9,further comprising a distributor for receiving the bits having higherpriority and the bits having relatively lower priority, distributing thereceived bits into a first bit stream comprised of the bits havinghigher priority and a second bit stream comprised of the bits havinghigher priority excluded from the first bit stream and the bits havingrelatively lower priority, such that the bits of the first bit stream isequal in number to the bits of the second bit stream, outputting thefirst bit stream to the first interleaver and outputting the second bitstream to the second interleaver.
 11. The apparatus as claimed in claim9, further comprising a parallel-to-serial (P/S) converter foroutputting output bits of the first interleaver and output bits of thesecond interleaver in series.
 12. The apparatus as claimed in claim 9,further comprising a controller for determining a modulation modeaccording to a radio channel state, and controlling the number of bitsof the bit stream mapped to one symbol based on the determinedmodulation mode.
 13. The apparatus as claimed in claim 9, wherein thebits having higher priority are systematic bits.
 14. The apparatus asclaimed in claim 13, wherein the bits having relatively lower priorityare parity bits.
 15. The apparatus as claimed in claim 10, wherein aratio of the bits having higher priority to the bits having relativelylower priority is ½, which is a coding rate of the encoder.
 16. Theapparatus as claimed in claim 10, wherein a ratio of the bits havinghigher priority to the bits having relatively lower priority is ¾, whichis a coding rate of the encoder.
 17. A method for receiving data of onesymbol represented by a bit stream comprised of at least 3 bits, the bitstream being comprised of a first bit part having higher reliability anda second bit part having relatively lower reliability, bits havinghigher priority being situated in the first bit part, bits havingrelatively lower priority being situated in the second bit part,comprising the steps of: demodulating the bits having higher prioritysituated in the first bit part and the bits having relatively lowerpriority situated in the second bit part; deinterleaving the demodulatedbits having higher priority; deinterleaving the demodulated bits havingrelatively lower priority; and decoding the deinterleaved bits havinghigher priority and the deinterleaved bits having relatively lowerpriority.
 18. The method as claimed in claim 17, further comprising thestep of receiving the demodulated bits having higher priority and thedemodulated bits having relatively lower priority, and dividing thereceived bits into two bit streams.
 19. The method as claimed in claim17, further comprising the step of receiving the deinterleaved bitshaving higher priority and the deinterleaved bits having relativelylower priority, classifying the received bits into the bits havinghigher priority and the bits having relatively lower priority, andoutputting the classified bits as one bit stream.
 20. The method asclaimed in claim 17, wherein the bits having higher priority aresystematic bits.
 21. The method as claimed in claim 20, wherein the bitshaving relatively lower priority are parity bits.
 22. An apparatus forreceiving data of one symbol represented by a bit stream comprised of atleast 3 bits, the bit stream being comprised of a first bit part havinghigher reliability and a second bit part having relatively lowerreliability, bits having higher priority being situated in the first bitpart, bits having relatively lower priority being situated in the secondbit part, comprising: a demodulator for demodulating the bits havinghigher priority situated in the first bit part and the bits havingrelatively lower priority situated in the second bit part; a firstdeinterleaver for deinterleaving the demodulated bits having higherpriority; a second deinterleaver for deinterleaving the demodulated bitshaving relatively lower priority; and a decoder for decoding thedeinterleaved bits having higher priority and the deinterleaved bitshaving relatively lower priority.
 23. The apparatus as claimed in claim22, further comprising a serial-to-parallel (S/P) converter forreceiving the demodulated bits having higher priority and thedemodulated bits having relatively lower priority from the demodulator,and dividing the received bits into two bit streams.
 24. The apparatusas claimed in claim 22, further comprising a classifier for receivingthe deinterleaved bits having higher priority from the firstdeinterleaver and the deinterleaved bits having relatively lowerpriority from the second deinterleaver, classifying the received bitsinto the bits having higher priority and the bits having relativelylower priority, and outputting the classified bits as one bit stream.25. A data processing apparatus in a mobile communication system, fortransforming data comprised of bits having higher priority and bitshaving relatively lower priority, generated by an encoder at apredetermined coding rate, comprising: a memory physically divided intoa first region and a second region, for storing the bits having higherpriority in the first region and the bits having relatively lowerpriority in the second region; a controller for determining a ratio ofthe bits having higher priority to the bits having relatively lowerpriority based on a coding rate of the encoder and a modulation mode ofa modulator, reading the bits having higher priority and the bits havingrelatively lower priority from the first region and the second regionaccording to a predetermined interleaving pattern so as to secure thedetermined ratio; and the modulator for mapping the read bits havinghigher priority to a first bit part and the read bits having relativelylower priority to a second bit part, in mapping a bit stream comprisedof at least 3 bits to one symbol, the bit stream comprised of the firstbit part having higher reliability and the second bit part havingrelatively lower reliability.
 26. The data processing apparatus asclaimed in claim 25, wherein the bits having higher priority aresystematic bits.
 27. The data processing apparatus as claimed in claim26, wherein the bits having relatively lower priority are parity bits.28. A method for processing data comprised of bits having higherpriority and bits having relatively lower priority, generated by anencoder, using a memory physically divided into a first region and asecond region and a high-order modulator in which a bit stream comprisedof at least 3 bits represents one symbol and the bit stream is comprisedof a first bit part having higher reliability and a second bit parthaving relatively lower reliability, comprising the steps of: storingthe bits having higher priority in the first region and the bits havingrelatively lower priority in the second region; determining a ratio ofthe bits having higher priority to the bits having relatively lowerpriority based on a coding rate of the encoder and a modulation mode ofa modulator; reading the bits having higher priority from the firstregion according to a predetermined interleaving pattern so as to securethe determined ratio; reading the bits having relatively lower priorityfrom the second region according to the predetermined interleavingpattern so as to secure the determined ratio; modulating the bits havinghigher priority and the bits having relatively lower priority such thatthe read bits having higher priority are situated in the first bit partand the read bits having relatively lower priority are situated in thesecond bit part.
 29. The method as claimed in claim 28, wherein the bitshaving higher priority are systematic bits.
 30. The method as claimed inclaim 29, wherein the bits having relatively lower priority are paritybits.